1. Technical Field
The present invention relates to a duty cycle correction circuit of a delay locked loop (DLL) and a delay locked loop including the duty cycle correction circuit, and more particularly to a duty cycle correction circuit including a switching circuit and a delay locked loop (DLL) including the duty cycle correction circuit, for efficiently analyzing the cause of generation of a duty cycle error.
2. Description
Generally, a Delay Locked Loop (DLL) receives an external clock signal input from the outside of a system and generates an internal clock signal synchronized to the external clock signal. The system includes logic devices, semiconductor devices, etc., using the internal clock signal.
The DLL can be utilized in a cache memory device (instead of an SRAM device that is generally used) for increasing a data processing rate between a CPU and DRAM, or applied to a synchronous DRAM, a RAMBUS DRAM®, etc., as well as various types of logic devices.
The Double Data rate (DDR) technique has been developed for improving the bandwidth of a memory system. A DDR memory system uses the rising edge and falling edge of the internal clock signal. The duty cycle of the internal clock signal is an important factor for maintaining the maximum timing margin in a high performance memory system.
When the duty cycle of the internal clock signal is not maintained at exactly 50%, the deviation of the duty cycle from 50% reduces the timing margin of a high performance memory system. For this reason, an apparatus for compensating for distortion of the duty cycle due to changes of processes, voltages, and temperatures, is necessary. A duty cycle correction circuit utilized in a DLL is a circuit for correcting the duty cycle of the internal clock signal.
FIG. 1 is a block diagram of a conventional delay locked loop (DLL). Referring to FIG. 1, the DLL 100 includes a DLL core 110, a clock buffer 130, and a duty cycle correction circuit 150.
The DLL core 110, an essential part of the DLL, receives an external clock signal ECLK and generates an internal clock signal ICLK synchronized to the external clock signal ECLK.
The clock buffer 130 includes a plurality of serially interconnected inverters 131, 133, 135, . . . , 137, and buffers the internal clock signal ICLK to generate a reference clock signal CLK and a complementary reference clock signal CLKB.
The inverter 131 includes one PMOS transistor P1 and one NMOS transistor N1, which are serially connected between a source voltage VDD and a ground voltage VSS. The structures of the remaining inverters 133, 135, . . . , 137 are the same as that of the inverter 131. The process for generating the reference clock signal CLK and the complementary reference clock signal CLKB is well known in the art.
When the channel length to channel width ratio of the PMOS transistor P1 and NMOS transistor N1 is the same in each of the inverters 131, 133, 135, . . . , 137, then the clock buffer 130 can output differential reference clock signals CLK and CLKB having a duty cycle of 50%.
However, if the duty cycle of the differential reference clock signals CLK and CLKB becomes 45% or 55% (hereinafter, referred to as “case when a duty cycle error is generated”), or not exactly 50%, due to changes in a process, voltage, and temperature, then the timing margin of the high performance memory system is reduced.
To avoid this problem, the duty cycle correction circuit 150 converts the differential reference clock signals CLK and CLKB into duty cycle offset information DCC and DCCB, and feeds back the duty cycle offset information DCC and DCCB to the DLL core 110. Thus, the DLL core 110 controls the duty cycle of the internal clock signal ICLK to be exactly 50% in response to the duty cycle offset information DCC and DCCB.
Since the duty cycle correction circuit 150 always operates while the DLL 100 is operating, it is not known whether the differential reference clock signals CLK and CLKB having the 50% duty cycle are generated by the interaction of the clock buffer 130 and the duty cycle correction circuit 150, or by the greater operation of the clock buffer 130 rather than that of the duty cycle correction circuit 150.
Thus, when a duty cycle error is generated, it is impossible to correctly analyze whether the duty cycle error is generated by the clock buffer 130 or by the duty cycle correction circuit 150.
Therefore, it would be desirable to provide a duty cycle correction circuit and a delay locked loop (DLL) including the duty cycle correction circuit, where the DLL is capable of controlling its operation in order to correctly analyze the cause of a duty cycle error when a duty cycle error is generated in the DLL.
According to one aspect of the present invention, a duty cycle correction circuit of a delay locked loop comprises: a differential amplifier which receives and amplifies differential reference signals input from a first input terminal and a second input terminal, and outputs differential output signals to a first differential output terminal and a second differential output terminal; a first transmission circuit which is connected between the first differential output terminal and a first node, and transmits a signal of the first differential output terminal to the first node under the control of control signals; a second transmission circuit which is connected between the second differential output terminal and a second node, and transmits a signal of the second differential output terminal to the second node under the control of the control signals; a first storage unit which is connected between the first node and a ground voltage and stores a signal of the first node; a second storage unit which is connected between the second node and the ground voltage and stores a signal of the second node; and a switching circuit which connects the first node to a first output terminal and the second node to a second output terminal under the control of a switching control signal.
The switching circuit comprises: a third transmission circuit which transmits the signal of the first node to the first output terminal when a switching control signal has a deactivated state; a fourth transmission circuit which transmits the signal of the second node to the second output terminal when the switching control signal has the deactivated state; a first voltage supplying circuit which is connected between the first output terminal and the ground voltage, and supplies the ground voltage to the first output terminal when a switching control signal has an activated state; and a second voltage supplying circuit which is connected between the second output terminal and the ground voltage, and supplies the ground voltage to the second output terminal when the switching control signal has the activated state.
The first transmission circuit through the fourth transmission circuit each include a PMOS transistor and a NMOS transistor. The first storage unit and the second storage unit each include a MOS transistor.
According to another aspect of the present invention, a delay locked loop comprises: a DLL core which receives an external clock signal and generates an internal clock signal synchronized to the external clock signal; a buffer which buffers the internal clock signal and outputs differential reference clock signals; and a duty cycle correction circuit which generates first control signals having desired offsets corresponding to differences in the duty cycles of each of the differential reference clock signals, and outputs the first control signals to the DLL core under the control of a switching control signal, wherein the DLL core corrects a duty cycle of the internal clock signal under the control of the first control signals.
The delay locked loop further comprises a pad for receiving the switching control signal. The delay locked loop further comprises a mode register set for generating the switching control signal.
According to another yet aspect of the present invention, a duty cycle correction circuit, comprises: input terminal adapted to receive a pair of differential reference clock signals each having a duty cycle; integrating means for integrating each of the reference clock signals to produce a pair of control signals indicating the duty cycles of the differential reference clock signals; and switching means adapted to receive a switching control signal and in response thereto to selectively output the control signals when the switching control signal has a first state and to output a pair of fixed voltage signals when the switching control signal has a second state.